This invention relates to communication switches and data storage systems for use therewith, and more particularly, to a multiple queue bank balanced queue control system, architecture, and methodology.
Most current network switches utilize a single queuing memory control structure, where data in and out from one or more sources (e.g., Ethernet, ATM, etc.) and one or more output sources of the same or different types can be served by the single queue memory and control structure. One problem with the single queue memory and queue control system is that the queue system becomes a bottleneck, so that data flow can only be in to or out of the queue, that is the queue controller and queue memory provide for only unidirectional data transfer.
In accordance with the present invention, there is provided a balanced, shared multiple bank queue memory architecture with a queue control and management architecture providing for balanced queue memory utilization to prevent queue congestion and overflow problems, and to provide for queue control management providing for bidirectional simultaneous data flow permitting both input and output queuing to be performed concurrently.